The present invention generally relates to a bond pad structure on an integrated circuit chip and more particularly, relates to a bond pad structure on an integrated circuit chip that is supported by a multiplicity of vias arranged in at least two regions each having a density different from the other.
In the fabrication of semiconductor devices, an integrated circuit chip is assembled in a package during a final process step to complete the fabrication process. The package is then connected to a printed circuit board as part of a large circuit. To establish electrical communication with the integrated circuit chip, a wire bonding process can be used to connect a multiplicity of bond pads situated on the integrated circuit chip to the printed circuit board.
In a typical IC chip, active circuit elements such as transistors, resistors, etc., are formed in the central portion, i.e. the active region, of the chip while bond pads are normally arranged around the periphery of the active region such that active circuit elements are less likely to be damaged during a subsequent bonding process. When a wire bonding process is performed on a bond pad on an IC chip, the process entails the bonding of a gold or aluminum wire to the bond pad by fusing the two together with ultrasonic energy. The wire is then pulled away from the bond pad after the bond is formed. During the bonding of the gold wire to the pad and the pulling away of the wire from the pad, high mechanical stress is placed on the bond pad. When the bond pads are not properly formed, defects such as delamination from the underlying substrate have been encountered.
The delamination, or otherwise known as bond pad lift-off, occurs due to the fact that during the attachment process of a gold wire to a bond pad, a high level of mechanical stress is placed on the pad. It is also caused by the fact that a relatively large, heavy bond is placed on top of layers which may not have strong adhesion to the underlying layers. For instance, one factor that affects adhesion between the layers is the usage of a diffusion barrier layer formed of a material such as TiN for preventing aluminum diffusion into underlying conductive layers during subsequent high temperature processes. The diffusion barrier layer utilized, i.e., TiN, TiW or other alloys, does not have strong adhesion to the underlying oxide layer in the bond pad. This is one example of how the bond pad lift-off defect can occur.
Other processing parameters may also cause bond pad lift-off or delamination problem in semiconductor devices. For instance, low dielectric constant (low-k) materials have been used in recently developed semiconductor devices which causes adhesion problems between these low-k dielectric materials and the underlying oxide layers. The adhesion of these low-k dielectric materials, or inter-metal-dielectric (IMD) materials to oxide is poorer than that between oxide and oxide. However, the use of low-k dielectric materials, such as HSQ (hydrogen silsesquioxane) and MSQ (methyl silsesquioxane) is desirable in high performance semiconductor structures since thinner layers of the materials may be used as insulating layers due to their low-k characteristics. Another drawback of these low-k dielectric materials is their low thermal conductivity when compared to that of regular oxide. During a chip bonding process, the local temperature around a bond pad is significantly higher due to the poor thermal conductivity of the low-k dielectric material. The thermal stress caused by the poor thermal conductivity of IMD, in addition to the mechanical stresses caused by the bonding operation, may cause delamination of a low-k IMD layer from its underlying oxide layer.
In modern semiconductor devices that are designed specifically for high speed operation or for use in radio frequency circuits, it becomes highly desirable to use a single metal layer as the bond pad. The elimination of lower metal layers results in a smaller parasitic capacitance which is essential for such applications. In single metal layer bond pad applications, the pig bond pad lift-off defect becomes more severe due to poor adhesion of the single metal layer with the underlying dielectric layer. The single metal layer deposited on a dielectric layer no longer has the beneficial anchoring effect achieved in multiple metal layers. This is shown in FIGS. 1A, 1B and 1C.
FIG. 1A is an enlarged, cross-sectional view of a semiconductor device 10 formed with a bond pad 12 that has a multi-level metal structure. The bond pad 12 is constructed by four individual metal layers 14 connected therein between by a plurality of vias 16. The bond pad 12 is formed in a dielectric material layer 18 that is pre-deposited on a silicon substrate 20. The bond pad 12 is further covered along its edges by a passivation material layer 22.
As shown in FIG. 1A, the bond pad 12 is firmly anchored in the dielectric layer 18 by the multiple metal layers 14 which are interconnected by the plurality of vias 16. The adhesion between the bond pad 12 and the dielectric layer 18 is sufficiently strong for conducting a wire pull test or a ball shear test, shown in FIG. 1C.
On the other hand, in the single metal layer bond pad structure 24 shown in FIG. 1B for the semiconductor structure 30, the adhesion between the metal layer 26, the vias 16 and the dielectric layer 28, without the anchoring effect of the other metal layers, is weak. As a result, the bond pad structure 24 can not survive a wire pull bond test without delaminating from the dielectric layer 28. Furthermore, the single metal bond pad 24 may not survive a wire bonding process without the bond pad lift-off defect.
Others have attempted to solve the poor bondability problem of a bond pad on a low-k dielectric material layer by increasing the density, i.e. or the pitch, defined as the ratio between the diameter of the via and the spacing between the vias. The larger number of vias improves thermal conduction, or heat dissipation of the bond pad and furthermore, improves the mechanical strength of the bond pad due to the anchoring capability of the vias. This is shown in FIGS. 2A and 2B.
FIG. 2A illustrates a conventional method for increasing the pitch, or density, of vias 16 under a bond pad 24 from that shown in FIG. 2B wherein the vias 16 have a pitch of 1:3. However, while gaining the thermal conductivity, heat dissipation properties, and the mechanical bond strength due to the larger number of vias 16, the high density via used for bond pad 24 causes other processing problems. For instance, when the number of vias, and thus via openings, greatly increases, i.e. to a pitch of 1:1, the via openings may be etched through and connected to other via openings. As a result, there is no insulating oxide or low-k dielectric material left in-between the via openings. The process for laying out and forming via openings that are densely placed together further adds complexity to the fabrication process.
It is therefore an object of the present invention to provide a bond pad structure supported by a multiplicity of vias that does not have the drawbacks or shortcomings of the conventional bond pad structures.
It is another object of the present invention to provide a bond pad structure that is supported by a multiplicity of vias arranged in at least two regions each having a density that is different from the other.
It is a further object of the present invention to provide a bond pad structure that is supported by a multiplicity of vias arranged in at least three regions each having a density that is different from the other regions.
It is another further object of the present invention to provide a bond pad structure that is supported by a multiplicity of vias arranged in at least two regions wherein a via density in one region is at least two times the via density in the other region.
It is still another object of the present invention to provide a method for forming a bond pad structure that is supported by vias arranged in regions of different densities.
It is yet another object of the present invention to provide a method for forming a bond pad structure on top of a low-k dielectric material layer that is supported by a multiplicity of vias formed of Cu.
In accordance with the present invention, a bond pad structure that is supported by a multiplicity of vias arranged in at least two regions each having a via density different from the other, is provided.
In a preferred embodiment, a bond structure that is supported by a multiplicity of vias arranged in at least two regions each having a via density different than the other is provided which includes a layer of an insulating material; a first multiplicity of vias formed in a center region of the layer of insulating material having a first density; a second multiplicity of vias formed in a peripheral region of the layer of insulating material surrounding the center region that has a second density; and a conductive metal pad of generally rectangular shape that is formed on top of and connect to the first and second multiplicity of vias.
In the bond pad structure, the second density is at least two times of the first density, or the second density is about three times of the first density. The bond pad may further include a third multiplicity of vias formed in an outer peripheral region of the layer of insulating material surrounding the peripheral region that has a third density. The third density is at least two times of the second density. The layer of insulating material is formed of a dielectric material, such as silicon oxide or a low-k material that has a dielectric constant smaller than 4.0. The first and second multiplicity of vias may be formed of Cu. The first multiplicity of vias can be formed with a pitch larger than 1:2, while the second multiplicity of vias may be formed with a pitch smaller than 1:2.
The present invention is further directed to a method for forming a bond pad structure that is supported by vias arranged in regions of different via densities which can be carried out by the steps of first providing a pre-processed electronic substrate; then depositing an insulating material layer on the pre-processed electronic substrate; then forming a first multiplicity of via openings that has a first pitch in the insulating material layer; then forming a second multiplicity of via openings that has a second pitch surrounding the first multiplicity of via openings in the insulating material layer; filling the first and second multiplicity of via openings with a conductive metal forming a first and second multiplicity of vias; and forming a conductive metal pad on top of and connected to the first and second multiplicity of vias.
The method for forming a bond pad structure that is supported by vias arranged in regions of different densities may further include the step of depositing the insulating material layer from a material that has a dielectric constant smaller than 4.0. The method may further include the step of filling the first and second multiplicity of via openings with Cu. The method may further include the step of forming the conductive metal pad with Al. The second pitch is larger than the first pitch, or the second pitch is at least two times of the first pitch.
The present invention is still further directed to a bond pad structure that is supported by a multiplicity of vias arranged in at least three regions each having a via density different than the others which includes a layer of an insulating material; a first multiplicity of vias that are formed in a center region of the layer of insulating material that has a first density; a second multiplicity of vias formed in an inner peripheral region of the layer of insulating material surrounding the center region which has a second density; a third multiplicity of vias formed in an outer peripheral region of the layer of insulating material surrounding the inner peripheral region and has a third density; and a conductive metal pad of generally rectangular shape that is formed on top of and connect to the first and second multiplicity of vias.
In the bond pad structure that is supported by a multiplicity of vias arranged in at least three regions, the second density is larger than the first density, while the third density is larger than the second density. The layer of insulating material may have a dielectric constant smaller than 4.0. The first, second and third multiplicity of vias may be formed of Cu.